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In computer engineering , a hardware description language HDL is a specialized computer language used to describe the structure and behavior of electronic circuits , and most commonly, digital logic circuits. A hardware description language enables a precise, formal description of an electronic circuit that allows for the automated analysis and simulation of an electronic circuit. It also allows for the synthesis of an HDL description into a netlist a specification of physical electronic components and how they are connected together , which can then be placed and routed to produce the set of masks used to create an integrated circuit.
Offering a modern, updated approach to digital design, this much-needed book reviews basic design fundamentals before diving into specific details of design optimization.
Hardware description language
In computer engineering , a hardware description language HDL is a specialized computer language used to describe the structure and behavior of electronic circuits , and most commonly, digital logic circuits.
A hardware description language enables a precise, formal description of an electronic circuit that allows for the automated analysis and simulation of an electronic circuit. It also allows for the synthesis of an HDL description into a netlist a specification of physical electronic components and how they are connected together , which can then be placed and routed to produce the set of masks used to create an integrated circuit.
A hardware description language looks much like a programming language such as C or ALGOL ; it is a textual description consisting of expressions, statements and control structures. One important difference between most programming languages and HDLs is that HDLs explicitly include the notion of time. HDLs form an integral part of electronic design automation EDA systems, especially for complex circuits, such as application-specific integrated circuits , microprocessors , and programmable logic devices.
Due to the exploding complexity of digital electronic circuits since the s see Moore's law , circuit designers needed digital logic descriptions to be performed at a high level without being tied to a specific electronic technology, such as ECL , TTL or CMOS. HDLs were created to implement register-transfer level abstraction, a model of the data flow and timing of a circuit. There are different types of description in them: "dataflow, behavioral and structural".
Example of dataflow of VHDL:. HDLs are standard text-based expressions of the structure of electronic systems and their behaviour over time. Like concurrent programming languages, HDL syntax and semantics include explicit notations for expressing concurrency. However, in contrast to most software programming languages , HDLs also include an explicit notion of time, which is a primary attribute of hardware.
Languages whose only characteristic is to express circuit connectivity between a hierarchy of blocks are properly classified as netlist languages used in electric computer-aided design. HDL can be used to express designs in structural, behavioral or register-transfer-level architectures for the same circuit functionality; in the latter two cases the synthesizer decides the architecture and logic gate layout.
HDLs are used to write executable specifications for hardware. A program designed to implement the underlying semantics of the language statements and simulate the progress of time provides the hardware designer with the ability to model a piece of hardware before it is created physically.
It is this executability that gives HDLs the illusion of being programming languages , when they are more precisely classified as specification languages or modeling languages. Simulators capable of supporting discrete-event digital and continuous-time analog modeling exist, and HDLs targeted for each are available.
Generally, however, software programming languages do not include any capability for explicitly expressing time, and thus cannot function as hardware description languages. System Verilog is the first major HDL to offer object orientation and garbage collection. Using the proper subset of hardware description language, a program called a synthesizer, or logic synthesis tool , can infer hardware logic operations from the language statements and produce an equivalent netlist of generic hardware primitives [ jargon ] to implement the specified behaviour.
Digital logic synthesizers, for example, generally use clock edges as the way to time the circuit, ignoring any timing constructs. The ability to have a synthesizable subset of the language does not itself make a hardware description language.
The first hardware description languages appeared in the late s, looking like more traditional languages. Separate work done about at the University of Kaiserslautern produced a language called KARL "KAiserslautern Register Transfer Language" , which included design calculus language features supporting VLSI chip floorplanning [ jargon ] and structured hardware design. By the late s, design using programmable logic devices PLDs became popular, although these designs were primarily limited to designing finite state machines.
In , a request from the U. HDL simulation enabled engineers to work at a higher level of abstraction than simulation at the schematic level, and thus increased design capacity from hundreds of transistors to thousands. Synthesis tools compiled HDL source files written in a constrained format called RTL into a manufacturable netlist description in terms of gates and transistors.
Writing synthesizable RTL files required practice and discipline on the part of the designer; compared to a traditional schematic layout, synthesized RTL netlists were almost always larger in area and slower in performance [ citation needed ]. However, VHDL and Verilog share many of the same limitations, such as being unsuitable for analog or mixed-signal circuit simulation.
Specialized HDLs such as Confluence were introduced with the explicit goal of fixing specific limitations of Verilog and VHDL, though none were ever intended to replace them. Over the years, much effort has been invested in improving HDLs. A future revision of VHDL is also in development [ when? As a result of the efficiency gains realized using HDL, a majority of modern digital circuit design revolves around it. Most designs begin as a set of requirements or a high-level architectural diagram.
Control and decision structures are often prototyped in flowchart applications, or entered in a state diagram editor. The process of writing the HDL description is highly dependent on the nature of the circuit and the designer's preference for coding style.
Designers often use scripting languages such as Perl to automatically generate repetitive circuit structures in the HDL language. The HDL code then undergoes a code review, or auditing. In preparation for synthesis, the HDL description is subject to an array of automated checkers.
The checkers report deviations from standardized code guidelines, identify potential ambiguous code constructs before they can cause misinterpretation, and check for common logical coding errors, such as floating ports or shorted outputs. This process aids in resolving errors before the code is synthesized. In industry parlance, HDL design generally ends at the synthesis stage.
Once the synthesis tool has mapped the HDL description into a gate netlist, the netlist is passed off to the back-end stage. In general, as the design flow progresses toward a physically realizable form, the design database becomes progressively more laden with technology-specific information, which cannot be stored in a generic HDL description.
Finally, an integrated circuit is manufactured or programmed for use. Simulation allows an HDL description of a design called a model to pass design verification , an important milestone that validates the design's intended function specification against the code implementation in the HDL description.
It also permits architectural exploration. The engineer can experiment with design choices by writing multiple variations of a base design, then comparing their behavior in simulation. Thus, simulation is critical for successful HDL design. To simulate an HDL model, an engineer writes a top-level simulation environment called a test bench. An HDL simulator — the program that executes the testbench — maintains the simulator clock, which is the master reference for all events in the testbench simulation.
Events occur only at the instants dictated by the testbench HDL such as a reset-toggle coded into the testbench , or in reaction by the model to stimulus and triggering events. Modern HDL simulators have full-featured graphical user interfaces , complete with a suite of debug tools.
These allow the user to stop and restart the simulation at any time, insert simulator breakpoints independent of the HDL code , and monitor or modify any element in the HDL model hierarchy. Design verification is often the most time-consuming portion of the design process, due to the disconnect between a device's functional specification , the designer's interpretation of the specification, and the imprecision [ citation needed ] of the HDL language.
An HDL description can also be prototyped and tested in hardware — programmable logic devices are often used for this purpose. Hardware prototyping is comparatively more expensive than HDL simulation, but offers a real-world view of the design. Prototyping is the best way to check interfacing against other hardware devices and hardware prototypes. Historically, design verification was a laborious, repetitive loop of writing and running simulation test cases against the design under test.
As chip designs have grown larger and more complex, the task of design verification has grown to the point where it now dominates the schedule of a design team. Looking for ways to improve design productivity, the electronic design automation industry developed the Property Specification Language. In formal verification terms, a property is a factual statement about the expected or assumed behavior of another object.
Ideally, for a given HDL description, a property or properties can be proven true or false using formal mathematical methods. In practical terms, many properties cannot be proven because they occupy an unbounded solution space. However, if provided a set of operating assumptions or constraints, a property checker can prove or disprove certain properties by narrowing the solution space. The assertions do not model circuit activity, but capture and document the designer's intent in the HDL code.
In a simulation environment, the simulator evaluates all specified assertions, reporting the location and severity of any violations. In a synthesis environment, the synthesis tool usually operates with the policy of halting synthesis upon any violation.
Assertion based verification is still in its infancy, but is expected to become an integral part of the HDL design toolset. An HDL is grossly similar to a software programming language , but there are major differences. Most programming languages are inherently procedural single-threaded , with limited syntactical and semantic support to handle concurrency. HDLs, on the other hand, resemble concurrent programming languages in their ability to model multiple parallel processes such as flip-flops and adders that automatically execute independently of one another.
Any change to the process's input automatically triggers an update in the simulator's process stack. Both programming languages and HDLs are processed by a compiler often called a synthesizer in the HDL case , but with different goals.
For HDLs, "compiling" refers to logic synthesis ; the process of transforming the HDL code listing into a physically realizable gate netlist. The netlist output can take any of many forms: a "simulation" netlist with gate-delay information, a "handoff" netlist for post-synthesis placement and routing on a semiconductor die, or a generic industry-standard Electronic Design Interchange Format EDIF for subsequent conversion to a JEDEC -format file.
On the other hand, a software compiler converts the source-code listing into a microprocessor -specific object code for execution on the target microprocessor. As HDLs and programming languages borrow concepts and features from each other, the boundary between them is becoming less distinct.
However, pure HDLs are unsuitable for general purpose application software development, [ why? Yet as electronic systems grow increasingly complex, and reconfigurable systems become increasingly common, there is growing desire in the industry for a single language that can perform some tasks of both hardware design and software programming. SystemC is an example of such— embedded system hardware can be modeled as non-detailed architectural blocks black boxes with modeled signal inputs and output drivers.
The high level of abstraction of SystemC models is well suited to early architecture exploration , as architectural modifications can be easily evaluated with little concern for signal-level implementation issues. However, the threading model used in SystemC relies on shared memory , causing the language not to handle parallel execution or low-level models well. In their level of abstraction, HDLs have been compared to assembly languages. Annapolis Micro Systems , Inc. Several projects exist for defining printed circuit board connectivity using language based, textual-entry methods.
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Hardware description language
Offering a modern, updated approach to digital design, this much-needed book reviews basic design fundamentals before diving into specific details of design optimization. You begin with an examination of the low-levels of design, noting a clear distinction between design and gate-level minimization. The author then progresses to the key uses of digital design today, and how it is used to build high-performance alternatives to software. With this book by your side, you'll gain a better understanding of how to apply the material in the book to real-world scenarios. Book Site. How many runways in a particular airport? Click here to find out.
Hardware description language
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